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Singh, N.S.S. and Hamid, N.H. and Asirvadam, V.S. and Khalid, U. and Anwer, J. (2012) Evaluation of circuit reliability based on distribution of different signal input patterns. In: UNSPECIFIED.

Anwer, J. and Shaukat, S.F. and Khalid, U. and Hamid, N.H. (2012) Reliable area index: A novel approach to measure reliability of Markov Random Field based circuits. In: UNSPECIFIED.

Singh, N.S.S. and Hamid, N.H. and Asirvadam, V.S. and Khalid, U. and Anwer, J. (2012) Sensitivity analysis of Probability Transfer Matrix (PTM) on same functionality circuit architectures. In: UNSPECIFIED.

Anwer, J. and Khalid, U. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2012) A novel error-detection mechanism for digital circuits using Markov random field modelling. In: UNSPECIFIED.

Khalid, U. and Anwer, J. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2011) Determination of sensitive inputs of nanoscale digital circuits using Bayesian network analysis. In: UNSPECIFIED.

Khalid, U. and Anwer, J. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2011) Improvement in reliability by changing the deterministic inputs of nanoscale circuits. In: UNSPECIFIED.

Khalid, U. and Anwer, J. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2011) Reliability-evaluation of digital circuits using probabilistic computation schemes. In: UNSPECIFIED.

Khalid, U. and Anwer, J. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2010) Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling. In: UNSPECIFIED.

Anwer, J. and Fayyaz, A. and Masud, M.M. and Shaukat, S.F. and Khalid, U. and Hamid, N.H. (2010) Fault-tolerance and noise modelling in nanoscale circuit design. In: UNSPECIFIED.

Anwer, J. and Khalid, U. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2010) Highly noise-tolerant design of digital logic gates using Markov random field modelling. In: UNSPECIFIED.

Anwer, J. and Khalid, U. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2010) Joint and Marginal Probability analyses of Markov Random Field networks for digital logic circuits. In: UNSPECIFIED.