Sethi, M.A.J. and Hussin, F.A. and Hamid, N.H. (2017) Review of network on chip architectures. Recent Advances in Electrical and Electronic Engineering, 10 (1). pp. 4-29. ISSN 23520965
Full text not available from this repository.Abstract
Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm. Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade. © 2017 Bentham Science Publishers.
Item Type: | Article |
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Additional Information: | cited By 5 |
Uncontrolled Keywords: | Embedded systems; Network architecture; Quality of service, Buffer management; Fault-tolerant routing algorithm; Link-sharing; Network-on-chip(NoC); Switching techniques, Network-on-chip |
Depositing User: | Mr Ahmad Suhairi UTP |
Date Deposited: | 09 Nov 2023 16:21 |
Last Modified: | 09 Nov 2023 16:21 |
URI: | https://khub.utp.edu.my/scholars/id/eprint/9242 |