In order to achieve the less test generation complexity, design-for-testability (DFT) techniques are used which causes untestable paths to be testable. These testable path delays have no effect on circuit performance are called false paths. It has been contended that such false paths should not be detected for test generation to keep off the unnecessary decrease in production. This paper proposes an algorithm framework to deal with these false paths through identification for DFT test. Proposed framework uses an integrated functional RTL circuit, called assignment decision diagram (ADD) which target at structural-level. Identification is done by sensitizing, observability and propagation rules for unified functional RTL circuits. Proposed framework overcomes the limitation of several existing RTL based approaches, such as the need for explicit separation between controller and data path. The effectiveness of the framework algorithm is shown through lemma proof. © 2016 IEEE.