This paper investigates the challenges of a 3D-stacked system-on-chip testing, especially in terms of thermal problem. It is known that test power can be more than twice the intended power dissipation of the chip in the functional mode, for a single die. This problem is exacerbated when more than one dies are stacked on top of each other in a single package. Without proper test strategies, the thermal limit could be exceeded during test and this could permanently damage the possibly good chips. Using a heuristic approach, we proposed a set of rules that need to be followed when scheduling the core tests of each chip layer. These rules are based on the initial findings of 3D-chip test simulation using a commercial thermal simulation tool. Using these simple rules, it was found that up to 40 reduction in the peak temperature can be achieved when the thermal-aware test scheduling technique is employed. © 2010 IEEE.