As CMOS transistors continue to miniaturize beyond 20nm dimension, semiconductor industries would not be able to confirm the firmness (stability) in the performance of those nano-based transistors. As miniaturization continues, variability in the performance of those transistors becomes very prominent and they will keep on growing, making the CMOS transistors less and less reliable. Subsequently, this will affect the performance and degrades the reliability of circuit systems made-up of those transistors. Thus, we are inevitably faced with the question of how to build a reliable computing system out of unreliable nano-based CMOS transistors. To tackle this problem, several computational modeling frameworks have been developed for quantifying reliability of integrated circuit systems. However, these modeling approaches have computational complexity, which increases exponentially with the size of circuit systems, making the reliability evaluation process of very-large-scale-integrated (VLSI) systems with hundreds of millions of transistors becoming very time consuming and intractable. Therefore, to speed up the reliability analysis of larger circuit systems, this paper looks into the development of an auto-based computational modeling framework. It is developed based on the generalization of Boolean Difference-based Error Calculator (BDEC) model, known as one of the simplest and powerful reliability evaluation frameworks for fault-tolerant nano-computing. © 2015 N. S. S. Singh and D. L. C. Ching.