This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The proposed architecture does not store the required matrix for bit-wise multiplication and does not use cyclic shift of barrel shifter. The proposed architecture is investigated using code length below 1000 bits and implementation of high code rate R = 5/6 and code length between 1000 and 2000 bits. Even though this architecture is optimized for short code length, it is shown that the proposed architecture achieves information throughput of 30.178 Gbps and area of 2737 logic element when code length N = 1944 and code rate R = 5/6. © 2014 IEEE.