As integrated chip (IC) is one of the most essential components for communication devices, enhancing the integrity of hardware security is essential to prevent any security breach. Implantation of Hardware Trojan (HT) into the IC is one of the most threatening hardware security risks since most of the IC design and fabrication phases are outsourced to third-party foundries. Gate-level netlist inspection is utterly important as HT could be easily hidden among the primitives of the circuit which makes the detection challenging. Previously, HT detection methods for gate-level netlist were mainly based on either net testability or net's structural features. In this paper, we proposed to consolidate these two types of features into a single feature vector to train supervised machine learning classifiers. We also analyzed the performance of the classifiers based on different combinations of features using Minimum Redundancy and Maximum Relevance (mRMR) technique. Using the best feature combination, we achieved a 99.85 True Positive Rate (TPR), 99.95 True Negative Rate (TNR) and 99.90 accuracy (ACC). The results were validated using 10-fold cross-validation. © 2019 IEEE.