Mixed-size concurrency: ARM, POWER, C/C++11, and SC

by Flur, S, Sarkar, S, Pulte, C, Nienhuis, K, Maranget, L, Gray, KE, Sezgin, A, Batty, M, Sewell, P
Published 2016

Modelling the ARMv8 architecture, operationally: Concurrency and ISA

by Flur, S, Gray, KE, Pulte, C, Sarkar, S, Sezgin, A, Maranget, L, Deacon, W, Sewell, P
Published 2018

ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures

by Simner, B, Flur, S, Pulte, C, Armstrong, A, Pichon-Pharabod, J, Maranget, L, Sewell, P
Published 2020