Article

Assaad, M. and Alser, M.H. and Bermak, A. (2013) Design and characterization of low power and low noise truly all-digital clock and data recovery circuit for SERDES devices. Journal of Low Power Electronics, 9 (1). pp. 63-72. ISSN 15461998

Alser, M.H. and Assaad, M.M. and Hussin, F.A. (2013) A wide-range programmable frequency synthesizer based on a finite state machine filter. International Journal of Electronics, 100 (11). pp. 1546-1556. ISSN 00207217

Assaad, M. and Alser, M.H. (2012) Design of an all-digital synchronized frequency multiplier based on a dual-loop (D/FLL) architecture. VLSI Design, 2012. ISSN 1065514X

Conference or Workshop Item

Alser, M.H. and Assaad, M. and Hussin, F.A. and Yohannes, I. (2012) Design and FPGA implementation of PLL-based quarter-rate clock and data recovery circuit. In: UNSPECIFIED.

Alser, M.H. and Assaad, M.M. (2011) Design and modeling of low-power clockless serial link for data communication systems. In: UNSPECIFIED.