Article

Saeed Koko, I. and Agustiawan, H. (2009) Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform. IAENG International Journal of Computer Science, 36 (2). ISSN 1819656X

Conference or Workshop Item

Koko, I.S. and Agustiawan, H. (2009) Parallel pipelined VLSI architectures for lifting-based two-dimensional forward discrete wavelet transform. In: UNSPECIFIED.

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Saeed, I. and Agustiawan, H. (2008) High-speed and power efficient lifting-based VLSI architecture for two-dimensional discrete wavelet transform. In: UNSPECIFIED.

Koko, I.S. and Agustiawan, H. (2008) Pipelined lifting-based VLSI architecture for two-dimensional inverse discrete wavelet transform. In: UNSPECIFIED.

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Awaludin, I. and Saad, N. and Agustiawan, H. (2008) A prediction of oil demand in Malaysia using time series modeling approach. In: UNSPECIFIED.