TY  - CONF
KW  - Benchmark circuit; Circuit performance; Direct measures; Dynamic nature; Error modeling; Error probabilities; Execution time; Junction tree; Major factors; Output errors
KW  -  Bayesian networks; Digital integrated circuits; Distributed parameter networks; Engineering research; Inference engines; Innovation; Intelligent networks; Knowledge based systems; Random errors
KW  -  Probability
TI  - Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling
EP  - 351
AV  - none
N1  - cited By 6; Conference of 2010 8th IEEE Student Conference on Research and Development - Engineering: Innovation and Beyond, SCOReD 2010 ; Conference Date: 13 December 2010 Through 14 December 2010; Conference Code:83885
ID  - scholars984
Y1  - 2010///
SN  - 9781424486489
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-79951962570&doi=10.1109%2fSCORED.2010.5704037&partnerID=40&md5=c47eab335fd14c228fe012f1a1bbbc7e
N2  - The reliability of digital circuits is in question since the new scaled transistor technologies continue to emerge. The major factor deteriorating the circuit performance is the random and dynamic nature of errors encountered during its operation. Output-error probability is the direct measure of circuit's reliability. Bayesian networks error modeling is the approach used to compute error probability of digital circuits. In our paper, we have used this technique to compute and analyze the output error probability of LGSynth's C17 benchmark circuit. The simulations are based on MATLAB and show important relationships among output-error probability, execution time and number of priors involved in the analysis. ©2010 IEEE.
SP  - 348
CY  - Kuala Lumpur
A1  - Khalid, U.
A1  - Anwer, J.
A1  - Singh, N.
A1  - Hamid, N.H.
A1  - Asirvadam, V.S.
ER  -