eprintid: 9670
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/96/70
datestamp: 2023-11-09 16:36:19
lastmod: 2023-11-09 16:36:19
status_changed: 2023-11-09 16:29:32
type: conference_item
metadata_visibility: show
creators_name: Oni, J.-O.
creators_name: Hussin, F.A.
creators_name: Zakaria, N.
title: Fine-Grained Overhead Analysis Utilizing Atomic Instructions for Cross-ISA Dynamic Binary Translation on Multicore Processor
ispublished: pub
keywords: Atoms; Benchmarking; Program processors; Programmable logic controllers; System-on-chip, Atomic Instructions; Compilation techniques; Dynamic binary translation; Efficiency improvement; Heterogeneous multi-core systems; Optimization architecture; Optimization operation; Performance improvements, Multicore programming
note: cited By 0; Conference of 7th International Conference on Intelligent and Advanced System, ICIAS 2018 ; Conference Date: 13 August 2018 Through 14 August 2018; Conference Code:143005
abstract: Modern software processing often involving other apps while running active apps to fulfill task requirements, which have caused the increment of program processing time inside heterogeneous multicore system-on-chip (SoC) processor. For available core usage efficiency improvement, concurrent compilation techniques has been applied into mix modes of statically and dynamically Dynamic Binary Translation and Optimisation (DBTO) process, to better service the combined applications processing. This research deep dived into finer-grained DBTO overhead analysis, to provide categorization and characterization of overhead sources in breakdown stages during concurrent instruction processing. A dual-engine of translation and optimization architecture is constructed for finer management of start-up overheads. Helper functions, i.e. LoadLink/StoreCondition (LL/SC) are derived from atomic instructions, to create multiple helper thread supported by multiple host cores, for better instruction translation and optimization operation concurrently. Our experiment platform, evaluated through PARSEC-3.0 benchmark suite, showed performance improvement approaching 2.0x for apps based programs and 1.25x for kernel based programs, for x86 to X86-64 emulation. This technique explore performance beyond hardware and software only limitations, and possess great potential for future parallel program processing improvement. © 2018 IEEE.
date: 2018
publisher: Institute of Electrical and Electronics Engineers Inc.
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85059740955&doi=10.1109%2fICIAS.2018.8540622&partnerID=40&md5=828ff2de5f4512bb3c5406fe895cdd86
id_number: 10.1109/ICIAS.2018.8540622
full_text_status: none
publication: International Conference on Intelligent and Advanced System, ICIAS 2018
refereed: TRUE
isbn: 9781538672693
citation:   Oni, J.-O. and Hussin, F.A. and Zakaria, N.  (2018) Fine-Grained Overhead Analysis Utilizing Atomic Instructions for Cross-ISA Dynamic Binary Translation on Multicore Processor.  In: UNSPECIFIED.