@inproceedings{scholars9645,
            note = {cited By 1; Conference of 7th International Conference on Intelligent and Advanced System, ICIAS 2018 ; Conference Date: 13 August 2018 Through 14 August 2018; Conference Code:143005},
            year = {2018},
             doi = {10.1109/ICIAS.2018.8540569},
       publisher = {Institute of Electrical and Electronics Engineers Inc.},
         journal = {International Conference on Intelligent and Advanced System, ICIAS 2018},
           title = {Solid State Lighting Driver IC Modeling Using Behavioral Simulation Technique},
          author = {Marzuki, A. and Aziz, S. R. A. and Azni Zulkifli, T. Z.},
            isbn = {9781538672693},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85059772490&doi=10.1109\%2fICIAS.2018.8540569&partnerID=40&md5=481577101216b2b05a005be0a2c4d07f},
        keywords = {Computer hardware description languages; Fluorescence; Integrated circuits; Light emitting diodes; Modeling languages; Timing circuits, Artificial lighting; Behavioral simulation; Error amplifiers; Fluorescent lighting; Led technologies; Solid state lighting; Step-down dc-dc converters; System verifications, DC-DC converters},
        abstract = {Solid state lighting (SSL) technology has a potential to provide artificial lighting more efficiently, low cost and long-lasting alternatives to conventional incandescent and fluorescent lighting sources. As the LED technology evolves, the applications involving LEDs are innumerable and its varieties impose a clear demand on design of controllable SSL drivers. A step down DC-DC converter has a great performance as SSL driver that regulates the power to LED by supplying a constant amount of current. This paper introduces an SSL driver model using behavioral simulation technique. Behavioral modeling using Verilog-A language represents the top level models rather than actual transistor implementation of the circuit. The models have predicted the required voltage levels for the ramp signal and the error amplifier gain. The achieved maximum current ripple was less than 5 . This technique has great potential for faster and better system verification. {\^A}{\copyright} 2018 IEEE.}
}