eprintid: 9242
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/92/42
datestamp: 2023-11-09 16:21:12
lastmod: 2023-11-09 16:21:12
status_changed: 2023-11-09 16:14:37
type: article
metadata_visibility: show
creators_name: Sethi, M.A.J.
creators_name: Hussin, F.A.
creators_name: Hamid, N.H.
title: Review of network on chip architectures
ispublished: pub
keywords: Embedded systems; Network architecture; Quality of service, Buffer management; Fault-tolerant routing algorithm; Link-sharing; Network-on-chip(NoC); Switching techniques, Network-on-chip
note: cited By 5
abstract: Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm. Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade. © 2017 Bentham Science Publishers.
date: 2017
publisher: Bentham Science Publishers B.V.
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85025168334&doi=10.2174%2f2352096510666170425102503&partnerID=40&md5=23844758ad8a89822be6e6d5e8ac0cb8
id_number: 10.2174/2352096510666170425102503
full_text_status: none
publication: Recent Advances in Electrical and Electronic Engineering
volume: 10
number: 1
pagerange: 4-29
refereed: TRUE
issn: 23520965
citation:   Sethi, M.A.J. and Hussin, F.A. and Hamid, N.H.  (2017) Review of network on chip architectures.  Recent Advances in Electrical and Electronic Engineering, 10 (1).  pp. 4-29.  ISSN 23520965