TY  - JOUR
KW  - Embedded systems; Network architecture; Quality of service
KW  -  Buffer management; Fault-tolerant routing algorithm; Link-sharing; Network-on-chip(NoC); Switching techniques
KW  -  Network-on-chip
ID  - scholars9242
N2  - Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm. Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade. © 2017 Bentham Science Publishers.
IS  - 1
Y1  - 2017///
VL  - 10
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85025168334&doi=10.2174%2f2352096510666170425102503&partnerID=40&md5=23844758ad8a89822be6e6d5e8ac0cb8
A1  - Sethi, M.A.J.
A1  - Hussin, F.A.
A1  - Hamid, N.H.
JF  - Recent Advances in Electrical and Electronic Engineering
AV  - none
SP  - 4
TI  - Review of network on chip architectures
N1  - cited By 5
SN  - 23520965
PB  - Bentham Science Publishers B.V.
EP  - 29
ER  -