%0 Journal Article
%@ 23520965
%A Sethi, M.A.J.
%A Hussin, F.A.
%A Hamid, N.H.
%D 2017
%F scholars:9242
%I Bentham Science Publishers B.V.
%J Recent Advances in Electrical and Electronic Engineering
%K Embedded systems; Network architecture; Quality of service, Buffer management; Fault-tolerant routing algorithm; Link-sharing; Network-on-chip(NoC); Switching techniques, Network-on-chip
%N 1
%P 4-29
%R 10.2174/2352096510666170425102503
%T Review of network on chip architectures
%U https://khub.utp.edu.my/scholars/9242/
%V 10
%X Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm. Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade. © 2017 Bentham Science Publishers.
%Z cited By 5