relation: https://khub.utp.edu.my/scholars/9242/
title: Review of network on chip architectures
creator: Sethi, M.A.J.
creator: Hussin, F.A.
creator: Hamid, N.H.
description: Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm. Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade. © 2017 Bentham Science Publishers.
publisher: Bentham Science Publishers B.V.
date: 2017
type: Article
type: PeerReviewed
identifier:   Sethi, M.A.J. and Hussin, F.A. and Hamid, N.H.  (2017) Review of network on chip architectures.  Recent Advances in Electrical and Electronic Engineering, 10 (1).  pp. 4-29.  ISSN 23520965     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85025168334&doi=10.2174%2f2352096510666170425102503&partnerID=40&md5=23844758ad8a89822be6e6d5e8ac0cb8
relation: 10.2174/2352096510666170425102503
identifier: 10.2174/2352096510666170425102503