@article{scholars9242,
            year = {2017},
           pages = {4--29},
         journal = {Recent Advances in Electrical and Electronic Engineering},
       publisher = {Bentham Science Publishers B.V.},
             doi = {10.2174/2352096510666170425102503},
          number = {1},
            note = {cited By 5},
          volume = {10},
           title = {Review of network on chip architectures},
        abstract = {Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm. Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade. {\^A}{\copyright} 2017 Bentham Science Publishers.},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85025168334&doi=10.2174\%2f2352096510666170425102503&partnerID=40&md5=23844758ad8a89822be6e6d5e8ac0cb8},
        keywords = {Embedded systems; Network architecture; Quality of service, Buffer management; Fault-tolerant routing algorithm; Link-sharing; Network-on-chip(NoC); Switching techniques, Network-on-chip},
          author = {Sethi, M. A. J. and Hussin, F. A. and Hamid, N. H.},
            issn = {23520965}
}