eprintid: 900
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/09/00
datestamp: 2023-11-09 15:49:02
lastmod: 2023-11-09 15:49:02
status_changed: 2023-11-09 15:38:40
type: conference_item
metadata_visibility: show
creators_name: Yasri, I.
creators_name: Hamid, N.H.
creators_name: Yap, V.V.
title: Real-time video edge detection with the memory access improvement
ispublished: pub
keywords: Computation power; Data-path architecture; Finite state machines; Frames per seconds; Hardware accelerator architecture; Hardware accelerators; Memory access; Memory bandwidths; Read operation; Real time videos; Real-time video processing; Sobel edge detection; Standard definitions; Traffic management; Video rates; Video surveillance, Acceleration; Computer graphics; Edge detection; Hardware; Information management; Mathematical operators; Medical imaging; Memory architecture; Real time systems; Security systems; Video signal processing, Pipeline processing systems
note: cited By 1; Conference of 2010 International Conference on Intelligent and Advanced Systems, ICIAS 2010 ; Conference Date: 15 June 2010 Through 17 June 2010; Conference Code:84196
abstract: Real-time video processing is the basic requirement for applications such as video surveillance, traffic management and medical imaging. The high computation power is a requirement to support this operation. This requirement could be fulfilled by utilizing the hardware accelerator architecture for computation part. This paper presents the development of edge detection hardware accelerator architecture for real time video processing systems. The algorithm of Sobel edge detection operator is used to develop this hardware accelerator. The NTSC standard definition video is digitized at 720�480 with a video rate of 30 frames per second. To develop hardware accelerator datapath architecture the management of memory access is deployed and architecture based pipeline are made with the potential of improvements in acceleration to read the data pixel from memory. In addition, a finite state machine is used to ensure the hardware accelerator controls the sequence of derivative computation, write and read operations. Initial simulation shows that the hardware accelerator architecture manages to achieve approximately 75 memory bandwidth reduction compare to previous work 5.
date: 2010
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-79952772694&doi=10.1109%2fICIAS.2010.5716106&partnerID=40&md5=8cd69f0659c3928583726106ff0079a8
id_number: 10.1109/ICIAS.2010.5716106
full_text_status: none
publication: 2010 International Conference on Intelligent and Advanced Systems, ICIAS 2010
place_of_pub: Kuala Lumpur
refereed: TRUE
isbn: 9781424466238
citation:   Yasri, I. and Hamid, N.H. and Yap, V.V.  (2010) Real-time video edge detection with the memory access improvement.  In: UNSPECIFIED.