eprintid: 8976
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/89/76
datestamp: 2023-11-09 16:20:55
lastmod: 2023-11-09 16:20:55
status_changed: 2023-11-09 16:13:59
type: conference_item
metadata_visibility: show
creators_name: Hooi, L.Y.
creators_name: Hiung, L.H.
creators_name: Drieberg, M.
creators_name: Sebastian, P.
title: Configurable 2 bits per cycle successive approximation register for analog to digital converter on FPGA
ispublished: pub
keywords: Approximation theory; Comparator circuits; Comparators (optical); Cost effectiveness; Costs; Field programmable gate arrays (FPGA); Frequency converters; Reusability, analog; Analog to digital converters; Binary search; digital; Large scale productions; Successive approximation methods; Successive approximation register; Successive approximations, Analog to digital conversion
note: cited By 3; Conference of 6th International Conference on Intelligent and Advanced Systems, ICIAS 2016 ; Conference Date: 15 August 2016 Through 17 August 2016; Conference Code:125970
abstract: Analog-to-Digital Converter (ADC) technology has been advancing to achieve a balance between speeds, size and cost. Successive approximation register (SAR) ADC is very popular for medium-to-high resolution as it is small but has difficulties in achieving high speed while flash ADC is big and not cost effective. Also, for different purposes, ADC have different resolution requirement. Producing ADCs with different resolution increases cost if it is not used in large scale production. In this paper, we propose to solve the issues of speed, size and cost by presenting a configurable 2 bits per cycle successive approximation register (SAR) ADC for FPGA implementation based on modification from successive approximation method. This SAR utilizes three comparators, instead of one comparator in normal SAR ADC. This enables the SAR to convert 2 bits at a time hence, reducing the conversion time by half, while at the same time, the resolution of this presented SAR is configurable. This increases the reusability of this SAR ADC for various different requirements of resolution. The design is implemented on Altera DE2 board with Cyclone II FPGA at a clock rate of 50MHz and can be boosted to 136MHz. On average, N cycles is needed for 2N bit resolution. © 2016 IEEE.
date: 2017
publisher: Institute of Electrical and Electronics Engineers Inc.
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85011966285&doi=10.1109%2fICIAS.2016.7824120&partnerID=40&md5=3d7fc83d8e7ec9364c4374cdbdd4b73d
id_number: 10.1109/ICIAS.2016.7824120
full_text_status: none
publication: International Conference on Intelligent and Advanced Systems, ICIAS 2016
refereed: TRUE
isbn: 9781509008452
citation:   Hooi, L.Y. and Hiung, L.H. and Drieberg, M. and Sebastian, P.  (2017) Configurable 2 bits per cycle successive approximation register for analog to digital converter on FPGA.  In: UNSPECIFIED.