TY  - CONF
A1  - Shaheen, A.-U.-R.
A1  - Hussin, F.A.
A1  - Hamid, N.H.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85011990404&doi=10.1109%2fICIAS.2016.7824116&partnerID=40&md5=5536af025b78972519f54f88bc6b6b58
PB  - Institute of Electrical and Electronics Engineers Inc.
SN  - 9781509008452
Y1  - 2017///
TI  - False path identification algorithm framework for nonseparable controller-data path circuits
ID  - scholars8946
KW  - Delay circuits; Timing circuits
KW  -  Algorithm framework; Circuit performance; Decision diagram; False path identifications; Propagation rule; Structural levels; Test generation complexity; Test generations
KW  -  Design for testability
N1  - cited By 1; Conference of 6th International Conference on Intelligent and Advanced Systems, ICIAS 2016 ; Conference Date: 15 August 2016 Through 17 August 2016; Conference Code:125970
N2  - In order to achieve the less test generation complexity, design-for-testability (DFT) techniques are used which causes untestable paths to be testable. These testable path delays have no effect on circuit performance are called false paths. It has been contended that such false paths should not be detected for test generation to keep off the unnecessary decrease in production. This paper proposes an algorithm framework to deal with these false paths through identification for DFT test. Proposed framework uses an integrated functional RTL circuit, called assignment decision diagram (ADD) which target at structural-level. Identification is done by sensitizing, observability and propagation rules for unified functional RTL circuits. Proposed framework overcomes the limitation of several existing RTL based approaches, such as the need for explicit separation between controller and data path. The effectiveness of the framework algorithm is shown through lemma proof. © 2016 IEEE.
AV  - none
ER  -