%0 Journal Article
%@ 02181266
%A Shaheen, A.-U.-R.
%A Hussin, F.A.
%A Hamid, N.H.
%D 2017
%F scholars:8896
%I World Scientific Publishing Co. Pte Ltd
%J Journal of Circuits, Systems and Computers
%K Controllers; Cost reduction; Delay circuits; Electric fault currents; Integrated circuit testing; Pulse analyzing circuits; Reconfigurable hardware; Testing, At-speed testing; Fault coverages; Hybrid DFT method; In-process technology; Path delay fault; Register transfer level; Test application time; Testability, Design for testability
%N 2
%R 10.1142/S0218126617500219
%T A hybrid delay design-for-testability for nonseparable RTL controller-data path circuits
%U https://khub.utp.edu.my/scholars/8896/
%V 26
%X Path delay testing has become crucial nowadays due to the advancement in process technology. Only enhanced scan (ES) among the scan approaches provides a solution to test the path delay fault (PDF) with large area overhead and the long test application time. This paper proposes a hybrid DFT method for nonseparable controller-data path RTL circuits. A snooping system is introduced which reduces the test application time. It performs the PDF testing between the controller and data path, and for the not-Clear control lines in the data path. The proposed method shared primary inputs and outputs to overcome the extra pin. However, the area overhead for the proposed approach is slightly large for the circuit with a small bit-width data path, which reduced drastically by the increase in the bit-width. The proposed approach supports the at-speed testing and is based on the PDF model. The experimental results showed that the proposed approach reduces the area overhead and drastically reduces the test application time in comparison with the enhanced scan (ES) and hierarchical two-pattern testability (HTPT) approach. Moreover, the technique can achieve a fault coverage identical to that achieved by the ES technique. © 2017 World Scientific Publishing Company.
%Z cited By 0