relation: https://khub.utp.edu.my/scholars/8649/
title: Bio-inspired fault tolerant network on chip
creator: Sethi, M.A.J.
creator: Hussin, F.A.
creator: Hamid, N.H.
description: The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of �synaptogenesis� and �sprouting� have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99 compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04 and 72.42 respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44 and 88.10 respectively compared to the literature techniques of XY and Odd-Even. © 2017 Elsevier B.V.
publisher: Elsevier B.V.
date: 2017
type: Article
type: PeerReviewed
identifier:   Sethi, M.A.J. and Hussin, F.A. and Hamid, N.H.  (2017) Bio-inspired fault tolerant network on chip.  Integration, the VLSI Journal, 58.  pp. 155-166.  ISSN 01679260     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85018729534&doi=10.1016%2fj.vlsi.2017.04.004&partnerID=40&md5=c594c2f8551c074e6cc7f7f927a4fc10
relation: 10.1016/j.vlsi.2017.04.004
identifier: 10.1016/j.vlsi.2017.04.004