TY  - CONF
SN  - 9781424474561
Y1  - 2010///
EP  - 267
A1  - Hussin, F.A.
A1  - Yu, T.E.C.
A1  - Yoneda, T.
A1  - Fujiwara, H.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-79959200808&doi=10.1109%2fAPCCAS.2010.5774922&partnerID=40&md5=b5c31fa421d416ca3efb839101536cb8
AV  - none
CY  - Kuala Lumpur
SP  - 264
ID  - scholars860
TI  - RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC
KW  - Chip testing; Heuristic approach; Peak temperatures; Set of rules; Simple rules; stacked-chip testing; System-On-Chip testing; Test power; Test scheduling; Test strategies; Thermal limits; Thermal simulation tool; Thermal-safe test scheduling
KW  -  Application specific integrated circuits; Dies; Electronic equipment testing; Heuristic methods; Integrated circuits; Microprocessor chips; Programmable logic controllers; Scheduling; Three dimensional
KW  -  Testing
N2  - This paper investigates the challenges of a 3D-stacked system-on-chip testing, especially in terms of thermal problem. It is known that test power can be more than twice the intended power dissipation of the chip in the functional mode, for a single die. This problem is exacerbated when more than one dies are stacked on top of each other in a single package. Without proper test strategies, the thermal limit could be exceeded during test and this could permanently damage the possibly good chips. Using a heuristic approach, we proposed a set of rules that need to be followed when scheduling the core tests of each chip layer. These rules are based on the initial findings of 3D-chip test simulation using a commercial thermal simulation tool. Using these simple rules, it was found that up to 40 reduction in the peak temperature can be achieved when the thermal-aware test scheduling technique is employed. © 2010 IEEE.
N1  - cited By 7; Conference of 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 ; Conference Date: 6 December 2010 Through 9 December 2010; Conference Code:85160
ER  -