TY  - CONF
Y1  - 2010///
SN  - 9781424463558
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-78650374229&doi=10.1109%2fISSSE.2010.5606936&partnerID=40&md5=aa045b1b2abf2a04f750dc275759390a
A1  - Anwer, J.
A1  - Fayyaz, A.
A1  - Masud, M.M.
A1  - Shaukat, S.F.
A1  - Khalid, U.
A1  - Hamid, N.H.
VL  - 2
EP  - 447
CY  - Nanjing
AV  - none
N1  - cited By 3; Conference of 2010 International Symposium on Signals, Systems and Electronics, ISSSE2010 ; Conference Date: 17 September 2010 Through 20 September 2010; Conference Code:82752
N2  - Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost. The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded performance in low-scaled transistor operation of future CMOS technology models. This paper is destined to give an overview of all the major fault-tolerance techniques and noise models proposed so far. Summing and analysing all this work, we have divided the literature into three categories and discussed their applicability in terms of proposing circuit design modifications, finding output error probability or methods proposed to achieve highly accurate simulation results. © 2010 IEEE.
KW  - Circuit designers; Circuit designs; CMOS technology; Fault-tolerant; Integrated circuit designs; Nanoscale circuits; Noise modelling; Noise models; Output errors; Semiconductor industry; Simulation result; Transistor operation
KW  -  CMOS integrated circuits; Design; Fault tolerance; Probability; Quality assurance; Semiconductor device manufacture; Transistors
KW  -  Integrated circuit manufacture
ID  - scholars814
TI  - Fault-tolerance and noise modelling in nanoscale circuit design
SP  - 444
ER  -