eprintid: 732
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/07/32
datestamp: 2023-11-09 15:48:52
lastmod: 2023-11-09 15:48:52
status_changed: 2023-11-09 15:23:03
type: article
metadata_visibility: show
creators_name: Saeed Koko, I.
creators_name: Agustiawan, H.
title: Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
ispublished: pub
note: cited By 1
abstract: A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al.
date: 2009
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-67649405062&partnerID=40&md5=9954a40f8f88f1033facc22319738b8d
full_text_status: none
publication: IAENG International Journal of Computer Science
volume: 36
number: 2
refereed: TRUE
issn: 1819656X
citation:   Saeed Koko, I. and Agustiawan, H.  (2009) Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform.  IAENG International Journal of Computer Science, 36 (2).   ISSN 1819656X