%0 Journal Article
%@ 1819656X
%A Saeed Koko, I.
%A Agustiawan, H.
%D 2009
%F scholars:732
%J IAENG International Journal of Computer Science
%N 2
%T Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
%U https://khub.utp.edu.my/scholars/732/
%V 36
%X A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al.
%Z cited By 1