TY  - CONF
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84969858016&doi=10.1109%2fCircuitsAndSystems.2015.7394068&partnerID=40&md5=8b050288caf0bf0ac1e4fd65b2b23dad
EP  - 79
N2  - This paper describes a work in progress: ASH1, an 8-bit input/ output processor (IOP) that is designed to be able to perform USB operations. It has a stack-based architecture where most of the operations are done on the top elements of the stack. The instruction set consists of 17 14-bit instructions optimized for framing and driving software code. ASH1 communicates with the main processing unit (Master CPU) through a wishbone bus. It has been proven reliably at 50 MHz in an Altera Cyclone II FPGA device. With around 1400 FPGA slices and a maximum clock frequency of 90 MHz, ASH1 could make a good substitute for big USB IP Cores. Future work includes making ASH1 MAC Ethernet capable and USB2 compatible. © 2015 IEEE.
ID  - scholars7231
AV  - none
N1  - cited By 1; Conference of IEEE International Circuits and Systems Symposium, ICSyS 2015 ; Conference Date: 2 September 2015 Through 4 September 2015; Conference Code:119196
TI  - ASH1: A stack-based input/ output processor for USB operations
Y1  - 2016///
KW  - Altera cyclones; Clock frequency; Input output processors; Instruction set; Processing units; Software codes; stack; Work in progress
KW  -  Reconfigurable hardware
PB  - Institute of Electrical and Electronics Engineers Inc.
A1  - Al-Dujaili, A.
A1  - Hiung, L.H.
A1  - Tan, S.
SP  - 76
SN  - 9781479917310
ER  -