%0 Conference Paper
%A Al-Dujaili, A.
%A Hiung, L.H.
%A Tan, S.
%D 2016
%F scholars:7231
%I Institute of Electrical and Electronics Engineers Inc.
%K Altera cyclones; Clock frequency; Input output processors; Instruction set; Processing units; Software codes; stack; Work in progress, Reconfigurable hardware
%P 76-79
%R 10.1109/CircuitsAndSystems.2015.7394068
%T ASH1: A stack-based input/ output processor for USB operations
%U https://khub.utp.edu.my/scholars/7231/
%X This paper describes a work in progress: ASH1, an 8-bit input/ output processor (IOP) that is designed to be able to perform USB operations. It has a stack-based architecture where most of the operations are done on the top elements of the stack. The instruction set consists of 17 14-bit instructions optimized for framing and driving software code. ASH1 communicates with the main processing unit (Master CPU) through a wishbone bus. It has been proven reliably at 50 MHz in an Altera Cyclone II FPGA device. With around 1400 FPGA slices and a maximum clock frequency of 90 MHz, ASH1 could make a good substitute for big USB IP Cores. Future work includes making ASH1 MAC Ethernet capable and USB2 compatible. © 2015 IEEE.
%Z cited By 1; Conference of IEEE International Circuits and Systems Symposium, ICSyS 2015 ; Conference Date: 2 September 2015 Through 4 September 2015; Conference Code:119196