eprintid: 720
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/07/20
datestamp: 2023-11-09 15:48:52
lastmod: 2023-11-09 15:48:52
status_changed: 2023-11-09 15:23:02
type: article
metadata_visibility: show
creators_name: Reaz, M.B.I.
creators_name: Lee, W.F.
creators_name: Hamid, N.H.
creators_name: Lo, H.H.
creators_name: Shakaff, A.Y.M.
title: High degree of testability using full scan chain and ATPG-An industrial perspective
ispublished: pub
keywords: Design for test; Design Methodology; Guideline; IC chips; Register transfer level; Scan chain; VLSI, Automatic test pattern generation; Integrated circuit testing; Integrated circuits, Design for testability
note: cited By 5
abstract: This study describes an efficient design methodology from an industrial perspective on utilizing Register Transfer Level (RTL) coding style, full scan chain implementation and Automatic Test Pattern Generation (ATPG) to achieve a high percentage of testability in the final Integrated Circuit (IC). The design methodology involves using an ASIC design flow with scan insertion and scan stitching performed after synthesis with scan flops set as don'tuse during synthesis process. Based on this method of ASIC design flow with the RTL coding style and guideline, an in-house 64 bit processor core that executes 3 instructions per cycle, is implemented with 0.35 micron process technology with a single scan chain of 4600 flip-flops, achieving an ATPG pattern for stuck-at at 100 test coverage and 99.81 fault coverage. Thus, creating high testability coverage with the ATPG pattern can be achieved by having a fully synchronous design using the proposed RTL coding style and full scan chain implementation. This study also describes the work around methods used when dealing with cost reduction involving reduction of test pin on the IC chip package. © 2009 Asian Network for Scientific Information.
date: 2009
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-67649780535&doi=10.3923%2fjas.2009.2613.2618&partnerID=40&md5=1dee6cfda34a45a2eda268e883b7b743
id_number: 10.3923/jas.2009.2613.2618
full_text_status: none
publication: Journal of Applied Sciences
volume: 9
number: 14
pagerange: 2613-2618
refereed: TRUE
issn: 18125654
citation:   Reaz, M.B.I. and Lee, W.F. and Hamid, N.H. and Lo, H.H. and Shakaff, A.Y.M.  (2009) High degree of testability using full scan chain and ATPG-An industrial perspective.  Journal of Applied Sciences, 9 (14).  pp. 2613-2618.  ISSN 18125654