@inproceedings{scholars6108,
            note = {cited By 0; Conference of 7th International Conference on Information Technology and Electrical Engineering, ICITEE 2015 ; Conference Date: 29 October 2015 Through 30 October 2015; Conference Code:119463},
            year = {2015},
             doi = {10.1109/ICITEED.2015.7408997},
       publisher = {Institute of Electrical and Electronics Engineers Inc.},
         journal = {Proceedings - 2015 7th International Conference on Information Technology and Electrical Engineering: Envisioning the Trend of Computer, Information and Engineering, ICITEE 2015},
           title = {Delay design-for-testability for functional RTL circuits},
           pages = {494--499},
            isbn = {9781467378635},
          author = {Shaheen, A.-U.-R. and Hussin, F. A. and Hamid, N. H.},
        abstract = {Design-for-testability (DFT) reduces the test complexity of sequential register-transfer-level (RTL) circuits. Only enhanced scan technique from the scan based approaches guarantee two-pattern testability with a large area and test time overhead. This paper proposes a path delay DFT technique for functional RTL circuits. Data paths are modified into hierarchical single-port-change (SPC) two-pattern testable (TPT) paths. The state register of the controller is transformed into a parallel-scan register. A snooping mechanism for the control, status and the not clear control lines to register and multiplexer is presented. Control lines considered as the segment of the RTL data path, not clear control signals and status lines are snooped to test without affecting the functionality of the RTL circuit. Two observation multiplexers are inserted to support the testing of control lines, status lines, and the state register. The proposed approach is based on the path delay fault model and supports the hierarchical test generation. The results show that for the given circuit, the area overhead of the proposed method rapidly decreases with the increase in bit width of the circuit data path. The proposed technique performs at-speed testing with small test application time and can obtain the fault coverage as achieved with the enhanced scan method. {\^A}{\copyright} 2015 IEEE.},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-84966570516&doi=10.1109\%2fICITEED.2015.7408997&partnerID=40&md5=e785339cc2b5ab362d54d9b80623c537},
        keywords = {Delay circuits; Integrated circuit testing; Multiplexing; Multiplexing equipment; Reconfigurable hardware; Testing; VLSI circuits, Delay path; Enhanced scan; Hierarchical; Register transfer level; VLSI, Design for testability}
}