eprintid: 6000
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/60/00
datestamp: 2023-11-09 16:17:45
lastmod: 2023-11-09 16:17:45
status_changed: 2023-11-09 16:04:31
type: article
metadata_visibility: show
creators_name: Mohammadat, M.T.
creators_name: Ali, N.B.Z.
creators_name: Hussin, F.A.
creators_name: Zwolinski, M.
title: Resistive open faults detectability analysis and implications for testing low power nanometric ICs
ispublished: pub
keywords: Electric power supplies to apparatus, Delay faults; Detectability; Low-power design; Resistive open; variability, Integrated circuit interconnects
note: cited By 2
abstract: Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost. © 1993-2012 IEEE.
date: 2015
publisher: Institute of Electrical and Electronics Engineers Inc.
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85028167359&doi=10.1109%2fTVLSI.2014.2312357&partnerID=40&md5=4223a475ce8fe75f1283bb08f2e1cb4b
id_number: 10.1109/TVLSI.2014.2312357
full_text_status: none
publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
volume: 23
number: 3
pagerange: 580-583
refereed: TRUE
issn: 10638210
citation:   Mohammadat, M.T. and Ali, N.B.Z. and Hussin, F.A. and Zwolinski, M.  (2015) Resistive open faults detectability analysis and implications for testing low power nanometric ICs.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23 (3).  pp. 580-583.  ISSN 10638210