TY  - JOUR
PB  - Institute of Electrical and Electronics Engineers Inc.
SP  - 580
AV  - none
ID  - scholars6000
EP  - 583
SN  - 10638210
N2  - Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost. © 1993-2012 IEEE.
KW  - Electric power supplies to apparatus
KW  -  Delay faults; Detectability; Low-power design; Resistive open; variability
KW  -  Integrated circuit interconnects
IS  - 3
TI  - Resistive open faults detectability analysis and implications for testing low power nanometric ICs
VL  - 23
JF  - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
N1  - cited By 2
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85028167359&doi=10.1109%2fTVLSI.2014.2312357&partnerID=40&md5=4223a475ce8fe75f1283bb08f2e1cb4b
A1  - Mohammadat, M.T.
A1  - Ali, N.B.Z.
A1  - Hussin, F.A.
A1  - Zwolinski, M.
Y1  - 2015///
ER  -