%0 Journal Article
%@ 10638210
%A Mohammadat, M.T.
%A Ali, N.B.Z.
%A Hussin, F.A.
%A Zwolinski, M.
%D 2015
%F scholars:6000
%I Institute of Electrical and Electronics Engineers Inc.
%J IEEE Transactions on Very Large Scale Integration (VLSI) Systems
%K Electric power supplies to apparatus, Delay faults; Detectability; Low-power design; Resistive open; variability, Integrated circuit interconnects
%N 3
%P 580-583
%R 10.1109/TVLSI.2014.2312357
%T Resistive open faults detectability analysis and implications for testing low power nanometric ICs
%U https://khub.utp.edu.my/scholars/6000/
%V 23
%X Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost. © 1993-2012 IEEE.
%Z cited By 2