eprintid: 599
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/05/99
datestamp: 2023-11-09 15:48:44
lastmod: 2023-11-09 15:48:44
status_changed: 2023-11-09 15:22:47
type: conference_item
metadata_visibility: show
creators_name: Koko, I.S.
creators_name: Agustiawan, H.
title: Parallel pipelined VLSI architectures for lifting-based two-dimensional forward discrete wavelet transform
ispublished: pub
keywords: Discrete wavelets; Forward discrete wavelet transforms; JPEG 2000; Lifting schemes; Lossless; Parallel VLSI architectures; Pipelined architecture; Proposed architectures; Real-time application; Scan methods; Speed-up factors; VLSI architectures, Decoding; Digital image storage; Discrete wavelet transforms; Parallel architectures; Signal analysis, Signal processing
note: cited By 1; Conference of 2009 International Conference on Signal Acquisition and Processing, ICSAP 2009 ; Conference Date: 3 April 2009 Through 5 April 2009; Conference Code:79615
abstract: In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-D DWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed architectures is that they only require a total temporary line buffer (TLB) of size N and 3N in 5/3 and 9/7, respectively. © 2009 IEEE.
date: 2009
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-77949985901&doi=10.1109%2fICSAP.2009.23&partnerID=40&md5=74ee36253ced3ed70cc29f687c1b7207
id_number: 10.1109/ICSAP.2009.23
full_text_status: none
publication: 2009 International Conference on Signal Acquisition and Processing, ICSAP 2009
place_of_pub: Kuala Lumpur
pagerange: 18-25
refereed: TRUE
isbn: 9780769535944
citation:   Koko, I.S. and Agustiawan, H.  (2009) Parallel pipelined VLSI architectures for lifting-based two-dimensional forward discrete wavelet transform.  In: UNSPECIFIED.