relation: https://khub.utp.edu.my/scholars/599/
title: Parallel pipelined VLSI architectures for lifting-based two-dimensional forward discrete wavelet transform
creator: Koko, I.S.
creator: Agustiawan, H.
description: In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-D DWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed architectures is that they only require a total temporary line buffer (TLB) of size N and 3N in 5/3 and 9/7, respectively. © 2009 IEEE.
date: 2009
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Koko, I.S. and Agustiawan, H.  (2009) Parallel pipelined VLSI architectures for lifting-based two-dimensional forward discrete wavelet transform.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-77949985901&doi=10.1109%2fICSAP.2009.23&partnerID=40&md5=74ee36253ced3ed70cc29f687c1b7207
relation: 10.1109/ICSAP.2009.23
identifier: 10.1109/ICSAP.2009.23