%P 519-523
%I IEEE Computer Society
%A S. Talpur
%A S.F. Khahro
%A A.M. Soomro
%A A.S. Saand
%V 2015-S
%T Improving router efficiency in network on chip triplet-based hierarchical interconnection network with shared buffer design
%J Proceedings - International Conference on Intelligent Systems, Modelling and Simulation, ISMS
%L scholars5732
%O cited By 0; Conference of 5th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2014 ; Conference Date: 27 January 2014 Through 29 January 2014; Conference Code:117206
%R 10.1109/ISMS.2014.95
%D 2015
%K Integrated circuit design; Integrated circuit interconnects; Intelligent systems; Network-on-chip; Routers; Servers, Cycle-accurate simulators; Fixed numbers; Packet latencies; Performance evaluation; Shared buffer; Simultaneous access; TBHIN; Virtual channels, Interconnection networks (circuit switching)
%X In Network on Chip effectiveness of router is dependent on the buffer locality, which makes the efficient flow control. Previous buffer design of Triplet-Based Hierarchical interconnection network (TBHIN) is standard, which leads to insufficient accessibility of this decisive resource, where each virtual channel owns a fixed number of buffers. In this article the design is implemented with sharing the buffers among the virtual channels, to improve the performance. The cyclic queue is allowed the simultaneous access to the shared buffer, which is one of the characteristics of TBHIN. A cycle-accurate simulator is used to obtain packet latency and throughput results for conventional and shared buffer designs. Simulation results illustrate that the packet latency is reduces up to 29 by shared buffer design in comparison to conventional buffer design. Also shared buffer design improves throughput up to 11.87 over the conventional buffer design. © 2014 IEEE.