%0 Conference Paper
%A Sethi, M.A.J.
%A Hussin, F.A.
%A Hamid, N.H.
%D 2014
%F scholars:4977
%I IEEE Computer Society
%K Algorithms; Digital signal processing, Average packet latencies; Bio-inspired algorithms; Bio-inspired techniques; Communication structures; Fault tolerant technique; Fault-tolerant; Network-on-chip(NoC); Processing elements, Network-on-chip
%R 10.1109/ICIAS.2014.6869449
%T Bio-inspired NoC fault tolerant techniques
%U https://khub.utp.edu.my/scholars/4977/
%X The incorporation of processing elements which include processor cores, memories, configurable components and DSP cores on Network on Chip (NoC) have made the communication structure of NoC very complex. To support the complexity of NoC, the physical device sizes are scaled down. However, the interconnects are not scaled at the same rate as the device. Interconnects have contributed to faults, system delay and high power consumptions. Interconnects of NoC are more vulnerable to faults. Many fault tolerant routing techniques have been proposed but they still have the energy, power, congestion problems and they lack the adaptiveness and robustness. In this work, two novel bio-inspired NoC techniques are analyzed. The bio-inspired mechanism of 'synaptogenesis' and 'sprouting' is adopted in the NoC algorithm and architecture. With the help of this the algorithm is robust and NoC is fault tolerant. In sprouting algorithm, the average throughput and average packet latency was increased by 8.56 and 4.65 respectively while average bandwidth was efficiently utilized by 0.23 as compared to synaptogenesis algorithm. The bio-inspired algorithms improved the average throughput and accepted traffic by 72.12 as compared to the literature technique. © 2014 IEEE.
%Z cited By 5; Conference of 2014 5th International Conference on Intelligent and Advanced Systems, ICIAS 2014 ; Conference Date: 3 June 2014 Through 5 June 2014; Conference Code:107042