TY  - CONF
KW  - Design for testability; System-on-chip
KW  -  DFT; Functional testing; Ieee 1500 standards; Intellectual property blocks; Mode of operations; Short periods; System on chips (SoC); Test access
KW  -  Integrated circuit testing
N1  - cited By 1; Conference of 2014 5th International Conference on Intelligent and Advanced Systems, ICIAS 2014 ; Conference Date: 3 June 2014 Through 5 June 2014; Conference Code:107042
Y1  - 2014///
A1  - Ali, G.
A1  - Hussin, F.A.
A1  - Ali, N.B.Z.
A1  - Hamid, N.H.
ID  - scholars4972
SN  - 9781479946549
TI  - Enhancement in IEEE 1500 standard for at-speed functional testing
AV  - none
CY  - Kuala Lumpur
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906330413&doi=10.1109%2fICIAS.2014.6869507&partnerID=40&md5=39e077f6adb39c7c458f2069ea8770df
N2  - System on chip (SOC) makes it possible to design a complex system in a short period of time by using intellectual property (IP) blocks. The complexity of the design makes testing of the SOC a very difficult task. To alleviate this test access issue, IEEE 1500 has been introduced. It has become a widely used option because of its completeness and easy to use approach, but this standard is only supported in the test mode as it stays transparent in normal functional mode. In this paper, an enhancement of the existing IEEE 1500 standard for functional testing, during functional mode of operation, is proposed. © 2014 IEEE.
PB  - IEEE Computer Society
ER  -