%0 Conference Paper
%A Socheatra, S.
%A Zain Ali, N.B.
%A Khir, M.H.Md.
%D 2014
%F scholars:4949
%I IEEE Computer Society
%K Eddy current testing, Contour plot; Induced magnetic fields; Induced voltages; Interconnect faults; Open faults; Potential faults; Printed circuit boards (PCB); Single fault, Printed circuit boards
%R 10.1109/ICIAS.2014.6869483
%T Printed circuit board interconnect fault inspection based on eddy current testing
%U https://khub.utp.edu.my/scholars/4949/
%X In this paper, a single fault (short or open) on a single sided printed circuit board (PCB) interconnect was experimented. The induced magnetic fields of faulty and fault free interconnects were detected by a planar array-coil sensor using eddy current testing (ECT) principle. The experimental results have shown that in the presence of a short fault, the differences between the induced voltages from fault free and faulty interconnects are highly negative in values. Whereas, in the presence of an open fault, the differences between the induced voltages from fault free and faulty interconnects are highly positive in values. These highly positive or negative induced voltages were translated into high density color regions on the contour plots. The potential fault positions can be located by observing the color regions of the contour plots with respect to each element of the array-coil sensor. © 2014 IEEE.
%Z cited By 1; Conference of 2014 5th International Conference on Intelligent and Advanced Systems, ICIAS 2014 ; Conference Date: 3 June 2014 Through 5 June 2014; Conference Code:107042