@article{scholars493,
           title = {New receiver architecture based on optical parallel interference cancellation for the optical CDMA},
             doi = {10.4304/jcm.3.1.64-70},
          number = {1},
            note = {cited By 9},
          volume = {3},
           pages = {64--70},
         journal = {Journal of Communications},
       publisher = {Academy Publisher},
            year = {2008},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-78651547402&doi=10.4304\%2fjcm.3.1.64-70&partnerID=40&md5=1dffbb77f24ff1ebac92c5462ad5177f},
        keywords = {Bandwidth; Code division multiple access; Computational complexity; Errors; Local area networks; Optical communication; Probability; Signal interference, Hardware complexity; Multiple Access Interference (MAI); Optical parallel interference cancellation, Fiber optic networks},
        abstract = {Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system, Based on the vast amount of bandwidth, OCDMA systems have received much attention in fiber optic Local Area Networks where the traffic is typically bursty. However, Multiple Access Interference (MAI), which is originated from other simultaneous users, severely limits the capacity of the system. Optical Parallel Interference Cancellation (OPIC) has been used to reduce the effect of MAI. However, the usage of OPIC in OCDMA systems will increase the demand for hardware complexity which results in higher processing time and cost. The hardware complexity increases in the receiver side of OPIC when the number of transmitter (users) increases. To overcome these difficulties, an efficient method is presented in this paper called, One Stage Optical Parallel Interference Cancellation (OS-OPIC) which is based mainly on the OPIC. Optical Orthogonal Code (OOC) is adopted as a signature sequence for the performance analysis and a new expression for the error probability is derived. It is shown that, the proposed method is effective to reduce the hardware complexity, processing time and cost while maintaining the same bit error probability at the cost of increasing threshold value. {\^A}{\copyright} 2008 Academy Publisher.},
          author = {Elfadel, N. and Aziz, A. A. and Saad, N. M.},
            issn = {17962021}
}