eprintid: 4925
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/49/25
datestamp: 2023-11-09 16:16:38
lastmod: 2023-11-09 16:16:38
status_changed: 2023-11-09 15:59:55
type: conference_item
metadata_visibility: show
creators_name: Anggraeni, S.
creators_name: Hussin, F.A.
creators_name: Jeoti, V.
title: Optimized encoder architecture for structured low density parity check codes of short length
ispublished: pub
keywords: Codes (symbols); Field programmable gate arrays (FPGA), Barrel shifters; encoder; Encoder architecture; Information bit; Low density parity check; Low-density parity-check (LDPC) codes; Proposed architectures; Structured codes, Architecture
note: cited By 1; Conference of 2014 5th International Conference on Intelligent and Advanced Systems, ICIAS 2014 ; Conference Date: 3 June 2014 Through 5 June 2014; Conference Code:107042
abstract: This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The proposed architecture does not store the required matrix for bit-wise multiplication and does not use cyclic shift of barrel shifter. The proposed architecture is investigated using code length below 1000 bits and implementation of high code rate R = 5/6 and code length between 1000 and 2000 bits. Even though this architecture is optimized for short code length, it is shown that the proposed architecture achieves information throughput of 30.178 Gbps and area of 2737 logic element when code length N = 1944 and code rate R = 5/6. © 2014 IEEE.
date: 2014
publisher: IEEE Computer Society
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906346399&doi=10.1109%2fICIAS.2014.6869526&partnerID=40&md5=e3e8069bf911ea67a8f1c29638509541
id_number: 10.1109/ICIAS.2014.6869526
full_text_status: none
publication: 2014 5th International Conference on Intelligent and Advanced Systems: Technological Convergence for Sustainable Future, ICIAS 2014 - Proceedings
place_of_pub: Kuala Lumpur
refereed: TRUE
isbn: 9781479946549
citation:   Anggraeni, S. and Hussin, F.A. and Jeoti, V.  (2014) Optimized encoder architecture for structured low density parity check codes of short length.  In: UNSPECIFIED.