eprintid: 4911
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/49/11
datestamp: 2023-11-09 16:16:37
lastmod: 2023-11-09 16:16:37
status_changed: 2023-11-09 15:59:53
type: conference_item
metadata_visibility: show
creators_name: Shaheen, A.-U.-R.
creators_name: Hussin, F.A.
creators_name: Hamid, N.H.
creators_name: Ali, N.B.Z.
title: Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
ispublished: pub
keywords: Boolean functions; Combinatorial circuits; Computer architecture, Automatic Generation; Conjunctive normal forms; Decision diagram; Instruction set architecture; Processor execution; Program generation; Register transfer level; Structural descriptions, Software testing
note: cited By 5; Conference of 2014 5th International Conference on Intelligent and Advanced Systems, ICIAS 2014 ; Conference Date: 3 June 2014 Through 5 June 2014; Conference Code:107042
abstract: This paper proposes a satisfiability-based automatic test instruction program generation to test the path delay faults using stuck-at fault in processor cores. Pre-computed test vectors are applied using the test instructions during normal processor execution. The proposed framework uses the assignment decision diagram (ADD) which represents the structural description of the register transfer level (RTL) circuit to extract the paths. ADD representation and instruction set architecture (ISA) information eliminates the paths that are untestable by the instructions during path extraction. The satisfiability (SAT)-solver is used to generate the sequence from conjunctive normal form (CNF) to find the justification/propagation paths. Test sequence is mapped to ISA to generate the test instruction program. A parwan processor module is used to validate our approach. © 2014 IEEE.
date: 2014
publisher: IEEE Computer Society
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906350466&doi=10.1109%2fICIAS.2014.6869530&partnerID=40&md5=4acc1a9593a3b00bf33b65139d9313d0
id_number: 10.1109/ICIAS.2014.6869530
full_text_status: none
publication: 2014 5th International Conference on Intelligent and Advanced Systems: Technological Convergence for Sustainable Future, ICIAS 2014 - Proceedings
place_of_pub: Kuala Lumpur
refereed: TRUE
isbn: 9781479946549
citation:   Shaheen, A.-U.-R. and Hussin, F.A. and Hamid, N.H. and Ali, N.B.Z.  (2014) Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram.  In: UNSPECIFIED.