eprintid: 450
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/04/50
datestamp: 2023-11-09 15:16:05
lastmod: 2023-11-09 15:16:05
status_changed: 2023-11-09 15:14:35
type: conference_item
metadata_visibility: show
creators_name: Saeed, I.
creators_name: Agustiawan, H.
title: High-speed and power efficient lifting-based VLSI architecture for two-dimensional discrete wavelet transform
ispublished: pub
keywords: 2-D DWT; Discrete wavelet transform; External-; Frame memory; Hardware utilization; High speeds; High-speed; International conferences; Lifting scheme; Lossless; Maximum power; Modelling and simulation; Performance evaluations; Pipelined; Pipelined architectures; Power consumption; Power-efficient; SCAN methods; Two-dimensional discrete wavelet transform; VLSI architecture; VLSI architectures, Alpha particle spectrometers; Asset management; Discrete wavelet transforms; Electric fault currents; Electric power utilization; Particle spectrometers; Two dimensional; VLSI circuits; Wavelet transforms, Architecture
note: cited By 2; Conference of 2nd Asia International Conference on Modelling and Simulation, AMS 2008 ; Conference Date: 13 May 2008 Through 15 May 2008; Conference Code:73202
abstract: Two lifting-based VLSI architectures for 2-D DWT for lossless 5/3 and lossy 9/7 algorithms were proposed by Ibrahim et al., based on two scan methods, overlapped and nonoverlaped. In the architecture based on the overlapped scan method, the maximum power consumption occurs due to overlap external frame memory access. On the other hand, in the nonoverlapped architecture, the power consumption was reduced to minimum by eliminating the overlapped areas which requires the addition of a line buffer of size N. Furthermore, the performance evaluations by Ibrahim el at., show that those pipelined architectures are optimal in terms of speedup, efficiency and hardware utilization. In this paper, we proposed new architecture, called intermediate architecture, for both 5/3 and 9/7 algorithms, which aim at reducing the power consumption of the overlapped areas, without using the expensive line buffer, to somewhat between the two extreme architectures proposed by Ibrahimt et al. © 2008 IEEE.
date: 2008
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-50249119659&doi=10.1109%2fAMS.2008.43&partnerID=40&md5=d4ab1f94117d54e404623295cf6a85bf
id_number: 10.1109/AMS.2008.43
full_text_status: none
publication: Proceedings - 2nd Asia International Conference on Modelling and Simulation, AMS 2008
place_of_pub: Kuala Lumpur
pagerange: 998-1005
refereed: TRUE
isbn: 9780769531366
citation:   Saeed, I. and Agustiawan, H.  (2008) High-speed and power efficient lifting-based VLSI architecture for two-dimensional discrete wavelet transform.  In: UNSPECIFIED.