TY  - CONF
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-50249119659&doi=10.1109%2fAMS.2008.43&partnerID=40&md5=d4ab1f94117d54e404623295cf6a85bf
A1  - Saeed, I.
A1  - Agustiawan, H.
EP  - 1005
Y1  - 2008///
SN  - 9780769531366
N1  - cited By 2; Conference of 2nd Asia International Conference on Modelling and Simulation, AMS 2008 ; Conference Date: 13 May 2008 Through 15 May 2008; Conference Code:73202
N2  - Two lifting-based VLSI architectures for 2-D DWT for lossless 5/3 and lossy 9/7 algorithms were proposed by Ibrahim et al., based on two scan methods, overlapped and nonoverlaped. In the architecture based on the overlapped scan method, the maximum power consumption occurs due to overlap external frame memory access. On the other hand, in the nonoverlapped architecture, the power consumption was reduced to minimum by eliminating the overlapped areas which requires the addition of a line buffer of size N. Furthermore, the performance evaluations by Ibrahim el at., show that those pipelined architectures are optimal in terms of speedup, efficiency and hardware utilization. In this paper, we proposed new architecture, called intermediate architecture, for both 5/3 and 9/7 algorithms, which aim at reducing the power consumption of the overlapped areas, without using the expensive line buffer, to somewhat between the two extreme architectures proposed by Ibrahimt et al. © 2008 IEEE.
KW  - 2-D DWT; Discrete wavelet transform; External-; Frame memory; Hardware utilization; High speeds; High-speed; International conferences; Lifting scheme; Lossless; Maximum power; Modelling and simulation; Performance evaluations; Pipelined; Pipelined architectures; Power consumption; Power-efficient; SCAN methods; Two-dimensional discrete wavelet transform; VLSI architecture; VLSI architectures
KW  -  Alpha particle spectrometers; Asset management; Discrete wavelet transforms; Electric fault currents; Electric power utilization; Particle spectrometers; Two dimensional; VLSI circuits; Wavelet transforms
KW  -  Architecture
ID  - scholars450
TI  - High-speed and power efficient lifting-based VLSI architecture for two-dimensional discrete wavelet transform
SP  - 998
CY  - Kuala Lumpur
AV  - none
ER  -