eprintid: 4402
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/44/02
datestamp: 2023-11-09 16:16:05
lastmod: 2023-11-09 16:16:05
status_changed: 2023-11-09 15:58:21
type: article
metadata_visibility: show
creators_name: Mohammadat, M.T.
creators_name: Ali, N.B.Z.
creators_name: Hussin, F.A.
creators_name: Zwolinski, M.
title: Multivoltage aware resistive open fault model
ispublished: pub
note: cited By 2
abstract: Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs causing delay failures and reliability-related concerns. The widespread utilization of multiple supply voltages in contemporary VLSI designs and emerging test methods poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the VDD effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observe that the detectable resistance range versus VDD varies with test speed. We consequently propose a voltage-aware model that divides the full range of open resistances into continuous behavioral intervals and three detectability ranges. The presented model is expected to substantially enhance multivoltage test generation and fault distinction. © 1993-2012 IEEE.
date: 2014
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84895058997&doi=10.1109%2fTVLSI.2013.2243926&partnerID=40&md5=e7b39d3c890a0e92812dee76a332984b
id_number: 10.1109/TVLSI.2013.2243926
full_text_status: none
publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
volume: 22
number: 2
pagerange: 220-231
refereed: TRUE
issn: 10638210
citation:   Mohammadat, M.T. and Ali, N.B.Z. and Hussin, F.A. and Zwolinski, M.  (2014) Multivoltage aware resistive open fault model.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2).  pp. 220-231.  ISSN 10638210