TY  - CONF
VL  - 1621
SN  - 0094243X
TI  - Superior model for fault tolerance computation in designing nano-sized circuit systems
SP  - 140
EP  - 148
Y1  - 2014///
N1  - cited By 0; Conference of 3rd International Conference on Fundamental and Applied Sciences: Innovative Research in Applied Sciences for a Sustainable Future, ICFAS 2014 ; Conference Date: 3 June 2014 Through 5 June 2014; Conference Code:112230
N2  - As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines. © 2014 AIP Publishing LLC.
A1  - Singh, N.S.S.
A1  - Asirvadam, V.S.
A1  - Muthuvalu, M.S.
AV  - none
ID  - scholars4134
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85150911031&doi=10.1063%2f1.4898458&partnerID=40&md5=c056cc779e382f21f91703cad27395ec
PB  - American Institute of Physics Inc.
ER  -