eprintid: 401
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/04/01
datestamp: 2023-11-09 15:16:02
lastmod: 2023-11-09 15:16:02
status_changed: 2023-11-09 15:14:28
type: conference_item
metadata_visibility: show
creators_name: Koko, I.S.
creators_name: Agustiawan, H.
title: Pipelined lifting-based VLSI architecture for two-dimensional inverse discrete wavelet transform
ispublished: pub
keywords: Architecture; Decoding; Digital image storage; Discrete wavelet transforms; Electrical engineering; Pinch effect; Pipeline processing systems; Strategic planning, Data-path architectures; Fully pipelined; Inverse discrete wavelet transform; JPEG2000; Lifting scheme; Pipelined VLSI architecture; Row processors; Symmetric extensions; Two-dimensional, Computer architecture
note: cited By 1; Conference of 2008 International Conference on Computer and Electrical Engineering, ICCEE 2008 ; Conference Date: 20 December 2008 Through 22 December 2008; Conference Code:75617
abstract: In this paper, high performance pipelined VLSI architectures for both inverse 5/3 and 9/7 filters and combined 5/3 and 9/7 are proposed. To ease architecture development the strategy adopted is to divide the details of the development into two steps each having less information to handle. In the first step, the external architecture, which is identical for both 5/3 and 9/7 and consists of a column-processor (CP) and a row-processor (RP), is developed. In the second step, fully pipelined column and row processors datapath architectures for 5/3 and 9/7 are developed separately that fit into CP and RP of the external architecture. The architecture also implements the symmetric extension algorithm recommended by JPEG2000. © 2008 IEEE.
date: 2008
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-62949167949&doi=10.1109%2fICCEE.2008.14&partnerID=40&md5=ec4e5b017ae8ee05ef7fbb7ab584ba93
id_number: 10.1109/ICCEE.2008.14
full_text_status: none
publication: Proceedings of the 2008 International Conference on Computer and Electrical Engineering, ICCEE 2008
place_of_pub: Phuket
pagerange: 692-700
refereed: TRUE
isbn: 9780769535043
citation:   Koko, I.S. and Agustiawan, H.  (2008) Pipelined lifting-based VLSI architecture for two-dimensional inverse discrete wavelet transform.  In: UNSPECIFIED.