eprintid: 3809
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/38/09
datestamp: 2023-11-09 15:52:05
lastmod: 2023-11-09 15:52:05
status_changed: 2023-11-09 15:47:40
type: conference_item
metadata_visibility: show
creators_name: Shaheen, A.-U.-R.
creators_name: Hussin, F.A.
creators_name: Hamid, N.H.
creators_name: Ali, N.B.Z.
title: Automatic generation of test instructions for structural faults in processor cores using satisfiability
ispublished: pub
keywords: ATPG; BCP; CNF; ISA; RTL; SAT; SBST, Computer architecture
note: cited By 1; Conference of 2013 International SoC Design Conference, ISOCC 2013 ; Conference Date: 17 November 2013 Through 19 November 2013; Conference Code:107260
abstract: Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework to generate the test program based on instructions set architecture (ISA) to test structural faults in processor cores. The proposed methodology framework made three major contributions. First, the use of effective conjunctive normal formula (CNF) encoding and instruction set architecture (ISA) prunes the combinational and sequential search space. Second, the modular based test generation and use of instruction set architecture (ISA) considerably reduces the test generation time. Third, an automatic generation of test instructions for structural faults. © 2013 IEEE.
date: 2013
publisher: IEEE Computer Society
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906913693&doi=10.1109%2fISOCC.2013.6864058&partnerID=40&md5=0181d1cd9643db86caa765e31bc1520f
id_number: 10.1109/ISOCC.2013.6864058
full_text_status: none
publication: ISOCC 2013 - 2013 International SoC Design Conference
place_of_pub: Busan
pagerange: 388-391
refereed: TRUE
isbn: 9781479911417
citation:   Shaheen, A.-U.-R. and Hussin, F.A. and Hamid, N.H. and Ali, N.B.Z.  (2013) Automatic generation of test instructions for structural faults in processor cores using satisfiability.  In: UNSPECIFIED.