TY  - CONF
EP  - 391
CY  - Busan
ID  - scholars3809
N1  - cited By 1; Conference of 2013 International SoC Design Conference, ISOCC 2013 ; Conference Date: 17 November 2013 Through 19 November 2013; Conference Code:107260
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906913693&doi=10.1109%2fISOCC.2013.6864058&partnerID=40&md5=0181d1cd9643db86caa765e31bc1520f
A1  - Shaheen, A.-U.-R.
A1  - Hussin, F.A.
A1  - Hamid, N.H.
A1  - Ali, N.B.Z.
KW  - ATPG; BCP; CNF; ISA; RTL; SAT; SBST
KW  -  Computer architecture
TI  - Automatic generation of test instructions for structural faults in processor cores using satisfiability
Y1  - 2013///
SN  - 9781479911417
N2  - Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework to generate the test program based on instructions set architecture (ISA) to test structural faults in processor cores. The proposed methodology framework made three major contributions. First, the use of effective conjunctive normal formula (CNF) encoding and instruction set architecture (ISA) prunes the combinational and sequential search space. Second, the modular based test generation and use of instruction set architecture (ISA) considerably reduces the test generation time. Third, an automatic generation of test instructions for structural faults. © 2013 IEEE.
AV  - none
PB  - IEEE Computer Society
SP  - 388
ER  -